1. Field of the Invention
The present invention pertains to analog-to-digital converters (ADCs), and more specifically, is directed to an apparatus and method used to pre-amplify the differential input signal in the comparator stage of a high-speed analog-to-digital converter (ADC).
2. Background Art
Applications such as high-end video signal processing, high performance digital communications, medical imaging, and the like, require analog-to-digital conversion with high sample rates and a large dynamic range. In response to these needs, there is a continued search for circuit architecture and techniques enabling an ADC to meet the specifications with reasonable chip size area and small power dissipation. It is of particular interest if such ADCs can be fabricated in standard CMOS technologies.
Most published ADCs that come close to the mentioned specifications are bipolar implementations. Their high speed and wide dynamic range owes to the use of open-loop precise, building blocks, including low-offset comparators. CMOS ADCs, by contrast, tend to use closed loop amplifier circuits for precise analog signal processing and close-loop, auto-zeroed, comparators in quantizers that resolve 4 bits or more. It is therefore difficult for CMOS circuits to attain the dynamic range of a bipolar ADC built with devices of comparable frequency capabilities. Implemented using comparable frequency capabilities the bipolar transistors are much faster than the CMOS transistors.
Another problem the high-speed ADCs implemented in CMOS technologies involves finite matching of the components on the chip. Specially, if small transistor sizes are used, then the mismatch results in large offset voltages. Such offset voltages have a substantial effect on differential non-linearity and the integral non-linearity of the ADC. Furthermore, electronic elements implemented using CMOS technologies have a reduced supply voltage because of the large electric field occurring in the device channels. A small reference voltage is required for such a system.
For example, a 0.18 micron (xcexcm) device can handle 1.8 volts (V), while for a 0.12 xcexcm device a 1.2V supply voltage is required. In a complex ADC of N bits, the number of quantization steps can be approximated by 2N. An N-bit ADC must use some form of multi-stage quantization with intermediate stages between each sub-quantize step to form and amplify the analog residue. With a reference voltage of 0.5 V, maximum quantization step size, has a value of 0.5/2N. Thus, a 10 bit converter (n=10), has quantization step size of 0.5 mV. The offset voltage due to mismatch in submicron technologies is typically much larger that this minimum step size. An offset compensation technique is therefore required to obtain a practically operating system.
The majority of the current high speed ADCs employ a 2.5 V supply voltage. Older versions of the high speed ADC employ higher voltage supply levels. For example, 3.8 V or 5V. The transition of the circuit towards lower values of the supply voltage is difficult to make. The reason for that is the direct proportionality that exist between the value of the supply voltage and the signal level. As the value of the supply voltage decreases the level of the signal decreases. As a consequence the level of noise associated with the signal decreases and the signal associated inaccuracies have to decrease. These factors impact the dynamic range of the ADC. In order to preserve the dynamic range of the ADC at its maximum level, it is desired to reduce the noise levels as much as possible.
In order to meet the requirements imposed by technology, the levels of the power supply have to be conveniently chosen, as discussed in one of the previous paragraphs. If the level of the supply voltage is low the correspondent power dissipation is low. But, the reduction of the level of supply voltage not necessarily mens the reduction of the noise levels which are strongly related with the dynamic range. In order to keep the dynamic range high the noise levels have to be kept low. We distinguish two categories of noises: the thermal noise and the voltage offset associated noises. The thermal noises are associated with the presence of a random type behavior of the currents and the voltages in the circuit. In an ideal case the offset voltage in transistors are absent form the circuits. But the presence of random voltages causes deviation from the ideal behavior. The presence of deviation is indicated by noise. If the value of the supply voltage decreases the value of the offset voltage is also affected. The desired small offset levels and implicitly the wide dynamic range can not be achieved by reduction of the input power supply.
Other factors, such as the technology employed to implement the circuits and the nature of the transistors used, also come into play. In order to obtain a small offset voltage the transistors used have to have a larger gate area. This involves two disadvantages: the larger chip area required to implement such circuits, and the greater power supply level required to operate these transistors. Also, the speed of the circuits does not improve with the reduction of the power supply.
Therefore, what are needed is a technique that achieves reduction of the offset voltage values, without focusing on adjusting the size of the gate area.
The present invention is directed to a method of reducing the value of offset voltage, from the comparator block in a high speed ADC.
The method involves pre-amplifying a plurality of reference voltage signals generated from a reference voltage generator in an ADC, prior being fed into a comparator block.
These and other objects are provided, according to the present invention, by a method and apparatus for converting an analog input signal to a N-bit digital output signal. First, a plurality of reference voltage signals is generated. The difference between each of the plurality of reference voltage signals and an analog input signal is pre-amplified separately. For this purpose a plurality of cascaded, differential, switched capacitor circuits is used. The switched-capacitor circuits output a plurality of pre-amplified difference signals. Each of the pre-amplified difference signals are compared to zero-crossings. A binary 1 or a binary 0 is assigned to each compared, pre-amplified signal. The binary 1""s and 0""s are encoded to form an M-bit encoded signal. The M-bit encoded signal is decoded to output an N-bit digital output signal.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.